Design Of An Efficient Switching Circuit For Low-Power Applications

Abstract

The escalating demand for computing power, coupled with the power limitations of portable, battery-operated devices, renders low-power memory an increasingly vital component. The power consumption of SRAM is significantly influenced by its access frequency. The power consumption of certain integrated circuits (ICs) can attain several watts at maximum bandwidth, exhibiting power demands comparable to dynamic RAM when functioning at elevated frequencies. Conversely, static random access memory (RAM) exhibits minimal power consumption, often nearing negligible levels—typically only a few microwatts—while idle, particularly when utilized with microprocessors operating at lower clock speeds. Power consumption in SRAM-based memory systems has been managed using several methods. This paper describes a dependable adiabatic SRAM. The primary purpose is to employ adiabatic switching circuits to achieve medium throughput for SRAM, hence compensating for throughput loss. Adiabatic switching constitutes the basis of the proposed design. To evaluate the proposed adiabatic SRAM, OrCAD PSpice is utilized. The data indicate that adiabatic SRAM surpasses all other SRAM variants in current use.